Nan Wu

H. Wang, Y. Huang, P. Li, & N. Wu (2026). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Abstract: Fast and accurate evaluation of hardware design quality is essential for agile hardware development. Traditional EDA tools, however, often impose a tradeoff between accuracy and runtime, limiting their effectiveness for modern, highly complex computing systems. In this context, directed graph representation learning (DGRL) has emerged as a powerful paradigm for encoding circuit netlists and computational graphs to enable surrogate modeling of hardware performance. However, DGRL remains relatively underexplored in the hardware domain, mainly due to the absence of comprehensive and user-friendly benchmarks. To address this gap, we present a benchmark that (1) includes six hardware design datasets and 15 prediction tasks spanning multiple levels of circuit abstraction, and (2) provides an extensive evaluation of 21 DGRL models, incorporating diverse graph neural networks (GNNs) and graph transformers (GTs) enhanced with directed-graph-specific positional encodings (PEs). Our results highlight that bidirected (BI) message passing neural networks (MPNNs) and robust PEs significantly enhance model performance. Notably, the top-performing models include PE-enhanced GTs interleaved with BI-MPNN layers and BI-Graph Isomorphism Network, both surpassing baselines across the 15 tasks. Additionally, our investigation into out-of-distribution (OOD) performance emphasizes the urgent need to improve OOD generalization in DGRL models. This benchmark, implemented with a modular codebase, streamlines the evaluation of DGRL models for both hardware and ML practitioners.

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N Wu, Y Li, H Yang, H Chen, S Dai, C Hao, C Yu, Y Xie (2024). ACM Transactions on Design Automation of Electronic Systems, Vol. 29, Issue 4, pgs. 1-42

Abstract: With the ever-increasing hardware design complexity comes the realization that efforts required for hardware verification increase at an even faster rate. Driven by the push from the desired verification productivity boost and the pull from leap-ahead capabilities of machine learning (ML), recent years have witnessed the emergence of exploiting ML-based techniques to improve the efficiency of hardware verification. In this article, we present a panoramic view of how ML-based techniques are embraced in hardware design verification, from formal verification to simulation-based verification, from academia to industry, and from current progress to future prospects. We envision that the adoption of ML-based techniques will pave the road for more scalable, more intelligent, and more productive hardware verification.

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N Wu, Y Xie, C Hao (2022). IEEE 40th International Conference on Computer Design (ICCD)

Abstract: Despite the great advance achieved by electronic design automation (EDA) tools, there is still a long way towards hardware agile development, whose ultimate goal is to reduce chip development cycles from years to months or even weeks. Hardware development typically involves many optimization-evaluation iterations, indicating that (1) fast and accurate quality-of-result (QoR) evaluation and (2) efficient optimization, either independently or integrally, will conspicuously improve the development efficiency. Specifically, targeting high-level synthesis and logic synthesis, we investigate (1) the power of exploiting graph neural networks (GNNs) for generalizable and accurate performance predictions, (2) the efficacy of applying reinforcement learning (RL) for design exploration, and (3) the superiority of combining GNN and RL to solve EDA problems. Experimental results demonstrate the promises of infusing intelligence into design synthesis and EDA tools. On top of current endeavors, we summarize the challenges in the respective EDA contexts and the prospects toward next generation EDA tools.

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N. Wu, Y. Li, C. Hao, S. Dai, C. Yu, & Y. Xie (2023). 60th ACM/IEEE Design Automation Conference (DAC)

Abstract:Reasoning high-level abstractions from bit-blasted Boolean networks (BNs) such as gate-level netlists can significantly benefit functional verification, logic minimization, datapath synthesis, malicious logic identification, etc. Mostly, conventional reasoning approaches leverage structural hashing and functional propagation, suffering from limited scalability and inefficient usage of modern computing power. In response, we propose a novel symbolic reasoning framework exploiting graph neural networks (GNNs) and GPU acceleration to reason high-level functional blocks from gate-level netlists, namely Gamora, which offers high reasoning performance w.r.t exact reasoning algorithms, strong scalability to BNs with over 33 million nodes, and generalization capability from simple to complex designs. To further demonstrate the capability of Gamora, we also evaluate its reasoning performance after various technology mapping options, since technology-dependent optimizations are known to make functional reasoning much more challenging. Experimental results show that (1) Gamora reaches almost 100% and over 97% reasoning accuracy for carry-save-array (CSA) and Booth-encoded multipliers, respectively, with up to six orders of magnitude speedups compared to the state-of-the-art implementation in the ABC framework; (2) Gamora maintains high reasoning accuracy (>92%) in finding functional modules after complex technology mapping, and we comprehensively analyze the impacts on Gamora reasoning from technology mapping.

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